-- EASE/HDL begin --------------------------------------------------------------
-- 
-- Architecture 'structure' of entity 'intreg'.
-- 
--------------------------------------------------------------------------------
-- 
-- Copy of the interface declaration:
-- 
--   port(
--     INTERRUPT_ACK : in     std_logic;
--     Min_Begin_ebl : in     std_logic;
--     clk           : in     std_logic;
--     interrupt     : out    std_logic;
--     reset_n       : in     std_logic);
-- 
-- EASE/HDL end ----------------------------------------------------------------
architecture structure of intreg is
                                                                                
begin 
PROCESS(clk,reset_n) 
begin 

	IF reset_n = '0' THEN 
       interrupt <= '0';
  
  	ELSIF clk'EVENT AND clk = '1' THEN
  		IF INTERRUPT_ACK = '1' THEN
  		   interrupt <= '0';
  		ELSIF Min_Begin_ebl ='1' THEN
  			  interrupt <='1';    
  			  
  		 END IF;
  	END IF;
  			    
END PROCESS; 			        
  		   
  		    
    


end architecture structure ; -- of intreg

